A designer may assemble and simulate an electronic system in a high-level modeling system (HLMS), such as System Generator for DSP which is available from Xilinx, Inc. The electronic system may be simulated in the HLMS using software algorithms that model the behavior of the design blocks that comprise the electronic system. A simulation of the electronic system in the HLMS may separate the electronic system into parts that are each simulated on different simulation platforms. Co-simulation is a simulation of an electronic system that combines the separate simulations of certain parts of the electronic system on respective simulation platforms. For example, a co-simulation may emulate the behavior of one design block of the electronic system on a hardware co-simulation platform while the remainder of the electronic system is simulated on a software co-simulation platform, such as a general purpose computer. Using a hardware co-simulation platform to emulate a portion of an electronic system may dramatically accelerate the speed of simulating the entire electronic system.
For co-simulation of a design block on a hardware co-simulation platform, a software co-simulation platform may write stimuli to the input ports of the design block on the hardware co-simulation platform and read captured results from the output ports of the design block. System Generator for DSP may automatically generate an emulator for a selected design block together with a communication interface needed to transfer stimuli and results between software and hardware co-simulation platforms. During simulation of the electronic system, System Generator for DSP may also coordinate the operation of the software and hardware co-simulation platforms, including controlling the enabling and disabling of the clocking of the design block on the hardware co-simulation platform.
The communication interface between the software co-simulation platform and an arbitrary design block implemented on the hardware co-simulation platform may include a memory map that provides an interface to access the input and output ports of the design block. Each input and output port may be assigned a respective address in the memory map, and stimuli may be applied to the design block by writing input values to the appropriate addresses in the memory map and results may be obtained from the design block be reading output values from the appropriate addresses in the memory map. Thus, a software co-simulation platform may interact with a design block emulated on a hardware co-simulation platform by performing write and read operations to addresses in the address map.
A memory map may be implemented using multiplexers and address decoding logic. An excessive amount of resources may be required to implement the memory map. A large memory map may include long combinational logic paths and large fanouts for multiplexer select signals that limit the operating frequency of the emulation of the design block. In addition, because the address decoding logic is tied to the physical locations of the input and output ports of the design block in the hardware co-simulation platform, an excessive amount of interconnect resources may be required to connect the memory map to the ports of the design block.
The present invention may address one or more of the above issues.